Responsibilities:
* Hspice simulations on key circuit designs.
* Static Timing analysis using Prime-time and Nano-time
* Power bus EM/IR analysis using Totem
* Cadence Virtuoso Custom Layout integration
* Sign-off checks and full-chip level functional verification
* Being the reference resource for the entire team
Experience: Freshers
Job location: Across India
Position: Design Intern
How To Apply:
Apply Here
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